Conventional dynamic random access memories (DRAMs) allow for the fast access of data using a page mode access scheme. This means that with sense amplifiers already sensed, data are read from the selected amplifier simply by toggling the common address. Although in the past this has been sufficient, several problems have arisen with respect to this approach.
First, the amount of data available in one page is not enough. For a 64 MEG DRAM, only 8K bits of data are available if an 8K refresh cycle is used. For an 8 bit output DRAM, this represents only 1K words. Second, the page mode operation is interrupted by the need to do a data refresh of the DRAM. Thus, the operating system must allow for interruption of the page mode. For those systems in which one large high density DRAM is a substantial fraction of the total memory, this becomes a bigger problem. A need is therefore arisen for a DRAM which can appear as a fully static SRAM from the point of view of the I/O pins and column and row address pins.